Memory systems, such as dual in-line memory modules (DIMMs), may include plural memory ranks. A memory rank may comprise plural memory devices simultaneously available to a controller in any manner, typically by asserting a common chip select (CS) signal. Typically, plural ranks mounted on a DIMM share command/address (CA) signals. Two or more ranks cannot be accessed simultaneously because although the data signals for each memory device on a rank are separate, the data signals are shared between ranks. Plural ranks may coexist on a single DIMM, e.g., one rank, two ranks, four ranks, and so on. Each rank may have any number of individual memory devices of a variety of technologies, e.g., dynamic random access memory (DRAM).
Each rank is typically uniquely associated with a CS signal. A controller may select a particular rank to receive and respond to the CA signals by asserting the CS signal associated with the particular rank. In a memory system in which a DIMM comprises a first rank and a second rank, a first CS signal runs from the controller to the first rank and a second CS signal runs from the controller to the second rank. A controller selects the first rank or the second rank by asserting the first CS signal or the second CS signal, respectively. An additional CS signal will be necessary for each additional rank added to the DIMM, which may be inefficient in some circumstances and may adversely impact DIMM board design, particularly pin out layout and usage at an interface to the controller.